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Ordering number : EN4454A
CMOS LSI
LC8390M
16-Bits A/D and D/A Converters for Digital Audio Systems
Overview
The LC8390M combines two-channel D/A and A/D converters in a single chip.
Features
* A/D Converter Block -- Quadratic modulation -- 16-bits resolution -- Built-in aliasing noise prevention digital filter -- A/D converters for two channels built in (synchronized input when standard audio output is used) -- S/N = 80 dB, THD + N = 0.025% (typical, Acompensation filter used) -- Digital output: MSB first, forward packed, bit clock rates of 32, 48, and 64 Fs -- External integrator used. * D/A Converter Block -- 16x oversampling quadratic noise shaper + PWM -- 16-bits resolution -- D/A converters for two channels built in (synchronized output) -- S/N = 85 dB, THD + N = 0.03% (typical, Acompensation filter used) -- Digital input: MSB first, backward packed, bit clock rates of 32, 48, and 64 Fs -- Digital oversampling filters are not built in. * Built-in double-buffering serial I/O circuits. (These circuits support both standard audio I/O and I/O with arbitrary timing.) * Sampling frequencies of 48, 44.1, and 32 kHz
* Master clock: 512 Fs (24.576 MHz when fs = 48 kHz) or 384 Fs Notes: Only the A/D converters operate when 384 Fs is selected as the master clock. The D/A converters do not operate in this mode. Since the analog I/F and analog power supply pins are more susceptible to damage from static electricity than the other pins, extra care is required. Analog I/F pins: DZOUTL, ADL2, ADLVSS, ADLVDD, ADL3, DZOUTR, ADR2, ADRVSS, ADRVDD, ADR3, DALVSS, PWML, DALVDD, DARVSS, PWMR, DARVDD * Package: 30-pin MFP * Power supply: 5 V, single voltage, CMOS
Package Dimensions
unit: mm 3073A-MFP30S
[LC8390M]
SANYO: MFP30S
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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O3098HA (OT)/92194TH (OT)/92093JN B8-0036 No. 4454-1/12
LC8390M
Pin Assignment
Block Diagram
No. 4454-2/12
LC8390M
Pin Functions
Block A/D block Pin No. 5 3 4 2 6 11 9 10 8 12 26 25 24 1 7 D/A block 15 13 14 18 16 17 21 20 22 Control and other pins 30 19 23 28 27 29 Pin ADLVDD ADLVSS ADL1 ADL2 ADL3 ADRVDD ADRVSS ADR1 ADR2 ADR3 ADLRCK ADBCK ADDATA DZOUTL DZOUTR DALVDD DALVSS PWML DARVDD DARVSS PWMR DALRCK DABCK DADATA DVDD DVSS CLKIN CLKCTL RESET TEST I/O -- -- I O O -- -- I O O I I O O O -- -- O -- -- O I I I -- -- I I I I Analog left channel A/D power supply Analog left channel A/D ground Left channel A/D audio input Left channel A/D linear output Left channel A/D quadratic output Analog right channel A/D power supply Analog right channel A/D ground Right channel A/D audio input Right channel A/D linear output Right channel A/D quadratic output A/D left and right channel clock input A/D bit clock input A/D data output A/D dithering clock output A/D dithering clock output Analog left channel D/A power supply Analog left channel D/A ground Left channel D/A PWM output Analog right channel D/A power supply Analog right channel D/A ground Right channel D/A PWM output D/A left and right channel clock input D/A bit clock input D/A data input Digital system power supply Digital system ground Master clock input Master clock selection (high: 512 Fs, low: 384 Fs) Reset input Test input. (This pin must be connected to DVDD during normal operation.) Function
No. 4454-3/12
LC8390M
Pin Types
Specification TTL output Circuit ADDATA Pin
Analog output
PWML, PWMR
ADL2, ADL3, DZOUTL, ADR2, ADR3, DZOUTR
Schmitt input
TEST, CLKCTL, ADLRCK, ADBCK, CLKIN, DADATA, DALRCK, DABCK
Analog input
ADL1, ADR1
Built-in pull-up resistor input
RESET
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum output voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VO max VIN max Pd max Topr Tstg Ta = -30 to +70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 200 -30 to +70 -40 to +125 Unit V V V mW C C
No. 4454-4/12
LC8390M
Allowable Operating Ranges at Ta = -30 to 70C, all VDD = 4.75 to 5.5 V, all VSS = 0 V unless otherwise specified
Ratings Parameter Operating supply voltage Input high level voltage Input low level voltage Frequency External clock input conditions Pulse width Rise and fall times Symbol VDD VIH VIL fEXT tEXTH tEXTL tEXTR tEXTF tRES tBCYC tBCW tBCS tBCH tDS tDH 70 70 ADBCK, DABCK, ADLRCK, and DALRCK: See figures 3 and 4. RESET: See figure 2. 15 cycles of the CLKIN input clock 325 100 70 70 DABCK and DADATA: See figure 3. ns ns ns ns ns ns CLKIN: See figure 1. All VDD pins*2 Schmitt inputs, built-in pull-up resistor inputs*1 Schmitt inputs, built-in pull-up resistor inputs*1 12.16 16 9 Conditions min 4.75 0.75 VDD 0.25 VDD 24.83 typ max 5.5 Unit V V V MHz ns ns
RESET low level input pulse width Transfer bit clock period Transfer clock input conditions Transfer bit clock pulse width Transfer bit clock setup time Transfer bit clock hold time D/A converter data input conditions Data setup time Data hold time
Note 1: TEST, CLKCTL, ADLRCK, ADBCK, CLKIN, DADATA, DALRCK, DABCK, RESET 2: Apply the same voltage to the DVDD, ADLVDD, ADRVDD, DALVDD and DARVDD pins.
Electrical Characteristics 1 at Ta = 25C, all VDD = 5.0 V, all VSS = 0 V unless otherwise specified
Ratings Parameter Total harmonic distortion A/D block Signal-to-noise ratio Crosstalk Total harmonic distortion D/A block Signal-to-noise ratio Crosstalk Symbol A-THD A-S/N A-C*T D-THD D-S/N D-C*T Conditions At 1 kHz and 0 dB * At 1 kHz and 0 dB* At 1 kHz and 0 dB* At 1 kHz and -1 dB* At 1 kHz and -1 dB* At 1 kHz and -1 dB* min typ 0.025 80 -78 0.03 85 -83 max Unit % dB dB % dB dB
Note: * A-compensation filter used, Fs = 48 kHz, and testing is performed using the Sanyo supplied evaluation board.
Electrical Characteristics 2 at Ta = -30 to 70C, all VDD = 4.75 to 5.5 V, all VSS = 0 V unless otherwise specified
Ratings Parameter Input low-level current Output high-level voltage Output low-level voltage Input leakage current Input and output capacitance Data output timing Data hold time Data delay time Symbol IIL VOH VOL ILK CIO tOH tOD IDD ADDATA: See figure 5. DVDD Current dissipation The sum of ADLVDD, ADRVDD, DALVDD and DARVDD. 0 50 7 8 14 16 Conditions RESET (built-in pull-up resistor inputs): VIN = VSS ADDATA: IOH = -0.4 mA ADDATA: IOL = 2 mA Schmitt inputs: VIN = VSS, VDD -10 min -250 4.0 0.4 +10 10 typ max Unit A V V A pF ns ns mA mA
No. 4454-5/12
LC8390M
Figure 1 External Clock Input Waveform (CLKIN)
Figure 2 RESET Input Waveform
Figure 3 Audio Data Input Conditions
No. 4454-6/12
LC8390M
Figure 4 Audio Clock Input Conditions
Figure 5 Audio Data Output Timing
Master Clock Setting
Set the CLKCTL pin to match the oscillator frequency as shown in the table below.
Oscillator frequency 512 Fs 384 Fs CLKCTL H L
Only the A/D converters operate when 384 Fs is selected. The D/A converters do not operate in this mode.
A/D Data Output Format
Always use the standard audio output mode when using this LSI in audio applications.
No. 4454-7/12
LC8390M Standard Audio Output
Arbitrary Timing Output
The output data pin (ADDATA) holds the left channel data when ADLRCK rises, and continues to output this value while ADLRCK remains high. Similarly, the right channel data is held when ADLRCK falls, and this value is output while ADLRCK remains low.
D/A Data Input Format
Always use the standard audio input mode when using this LSI in audio applications. Standard Audio Input
No. 4454-8/12
LC8390M Arbitrary Timing Input
The previous 16 bits of input data are valid on the rise or fall of DALRCK.
A/D Digital Filter Frequency Response (theory values, fs = 48 kHz)
Response (dB)
Frequency (kHz)
Operating Principles
1. A/D Converter Block The A/D converter block in this IC is a 2-channel 16-bit A/D converter that uses a quadratic modulation technique. The circuit includes two built-in modulators (although an external integrator is used), and the analog input signals are simultaneously sampled at a 128x sampling rate. The oversampled data is decimated using a digital filter. The output data is serial signed 16-bit two's complement data. When standard audio output is used, simultaneously sampled data is output. When arbitrary timing is used, left channel data is output on the rise of ADLRCK, and right channel data is output on the fall of ADLRCK. 2. D/A Converter Block The D/A converter block in this IC is a 2-channel 16-bit D/A converter that combines a quadratic noise shaper and PWM (pulse width modulation) techniques. Two PWM generators are built in, and quadratic noise shaping is applied to the data, which is oversampled by holding the previous value (note that digital filters are not built in), and output from the left and right channels at the same time. Input data is serial signed 16-bit two's complement data. Since digital oversampling filters are not built in, steep external low-pass filters (LPF) are required. Input data is acquired on the rising edge of DALRCK for both standard audio input and arbitrary timing input modes. Data is output from the PWM generators at the same time from the left and right channels.
No. 4454-9/12
LC8390M 3. Initialization The LC8390M must be initialized after power is applied and when the sampling period changes. To initialize the LC8390M, once the power supply voltage has stabilized and CLKIN has been supplied, a low level must be input to the RESET pin for a period longer than 15 CLKIN cycles.
Design and Usage Notes
1. External Clock The CLKIN must not be stopped during operation. If this clock is not supplied, overcurrents may occur since dynamic logic is used internally, and the LC8390M may function abnormally. This IC must synchronize its internal operating timing with the externally supplied ADLRCK and DALRCK. This synchronization is performed by resetting an internal counter. This reset is only performed a few times on the rising edges of ADLRCK and DALRCK following initialization by a RESET pin input. Therefore, the CLKIN, ADLRCK, ADBCK, DALRCK and DABCK clock inputs must be synchronized. However, CLKIN and other clocks do not have to be synchronized for arbitrary timing input and output. Clock jitter will degrade A/D and D/A converter precision in this IC. The wiring lines for the master clock must be kept as short as possible, and a crystal oscillator signal level clock should be used. 2. Power Supply and Ground Use care in supplying power and ground to this IC. Separate the analog and digital blocks, and provide a separate ground plane for each. Connect the analog and digital grounds to points near the power supply on the PC board. While DVDD is the power supply for the internal logic circuits, since DVDD and the analog system VDD supplies (ADLVDD, ADRVDD, DALVDD and DARVDD) are connected together through the IC substrate with a few Ohms resistance, they should have identical voltages, and care should be exercised in handling the digital system power supply. 3. A/D Block DC Offset Adjustment A DC offset component appears in the A/D block digital output due to manufacturing variations in the IC itself and in resistor values. When there is a DC offset, differences in the full scale level of the analog input are created. It is therefore necessary to adjust the DC offset adjustment point in the application circuit example (see the section "LC8390M Application Circuit Example") while monitoring the digital output, and to cut the DC component by performing HPF processing in the input processing block of the later stage DSP.
No. 4454-10/12
LC8390M
Unit (resistance: , capacitance: F)
Sample Application Circuit
No. 4454-11/12
LC8390M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 4454-12/12

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